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features sample frequencies from 4 khz to 50 khz 16-bit linear, 8-bit linear, m -law, or a-law audio data coding programmable gain for analog inputs programmable attenuation for analog outputs on-chip oscillators +5v power supply microphone and line level analog inputs headphone, speaker, and line outputs on-chip anti-aliasing/smoothing filters serial digital interface general description the CS4215 is a single-chip, stereo, cmos multime- dia codec that supports cd-quality music, fm radio-quality music, telephone-quality speech, and modems. the analog-to-digital and digital-to-analog converters are 64 oversampled delta-sigma converters with on-chip filters which adapt to the sample fre- quency selected. the +5v only power requirement makes the CS4215 ideal for use in workstations and personal computers. integration of microphone and line level inputs, input and output gain setting, along with headphone and monitor speaker driver, results in a very small footprint. ordering information: CS4215-kl 0 c to 70 c 44-pin plcc CS4215-kq 0 c to 70 c 100-pin tqfp cdb4215 evaluation board 16-bit multimedia audio codec semiconductor corporation CS4215 linl linr minl minr m u x sdin gain 8 xtl1in xtl1out xtl2in xtl2out cmout clkin clkout clock generator pio0 pio1 pdn va1 va2 vd1 vd2 agnd1 agnd2 dgnd1 dgnd2 control interface and registers a/d a/d reset d/c serial input/output sdout sclk fsync tsout tsin mout1 vref loutr loutl mout2 attenuator output d/a d/a voltage reference headl headr headc mute monitor attenuator + + m -law a-law encode unsigned m -law a-law decode unsigned sept 93 ds76f2 1 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445-7222 fax: (512) 445-7581 copyright ? crystal semiconductor corporation 1993 (all rights reserved) this data sheet was written for revision e CS4215 codecs and later. for differences between revision e and previous versions, see appendix a . the CS4215 is an mwave tm audio codec.
analog characteristics ( t a = 25 c; va1, va2, vd1, vd2 = +5v; input levels: logic 0 = 0v, logic 1 = vd1, vd2; full scale input sine wave, no gain, no attenuation 1 khz; conversion rate = 48 khz; no gain, no attenuation, sclk = 3.072 mhz; measurement bandwidth is 10 hz to 20 khz; slave mode; unless otherwise specified.) parameter * symbol min typ max units analog input characteristics - minimum gain setting (0 db); unless otherwise specified. adc resolution 16 - - bits adc differential nonlinearity - - 0.9 lsb instantaneous dynamic range line inputs idr 80 84 - db mic inputs 72 78 - db total harmonic distortion line inputs thd - - 0.012 % mic inputs - - 0.032 % interchannel isolation line to line inputs - 80 - db line to mic inputs - 60 - db interchannel gain mismatch line inputs - - 0.5 db mic inputs - - 0.5 db frequency response (note 1) (0 to 0.45 fs) -0.5 - +0.2 db programmable input gain line inputs -0.2 - 23.5 db mic inputs 19.8 - 44 db gain step size - 1.5 - db absolute gain step error - - 0.75 db offset error line inputs (ac coupled) - 150 400 with hpf = 0 line inputs (dc coupled) - 10 150 lsb (no gain) mic inputs - 400 - offset error line inputs (ac coupled) - 0 5 with hpf = 1 (notes 1,2) line inputs (dc coupled) - 0 5lsb (no gain) mic inputs - 0 5 full scale input voltage: (mlb=0) mic inputs 0.250 0.28 0.310 vpp (mlb=1) mic inputs 2.50 2.8 3.10 v pp line inputs 2.50 2.8 3.10 v pp gain drift - 100 - ppm/ c input resistance (note 3) 20 - - k w input capacitance - - 15 pf cmout output voltage (note 4) 1.9 2.1 2.3 v (maximum output current = 400 m a) specifications are subject to change without notice. * parameter definitions are given at the end of this data sheet. mwave ? is a trademark of the ibm corporation. notes: 1. this specification is guaranteed by characterization, not production testing. 2. very low frequency signals will be slightly distorted when using the hpf. 3. input resistance is for the input selected. non-selected inputs have a very high (>1m w ) input resistance. 4. dc current only. if dynamic loading exists, then cmout must be buffered or the performance of adc?s and dac?s may be degraded. CS4215 2 ds76f2
analog characteristics (continued) parameter * symbol min typ max units analog output characteristics - minimum attenuation; unless otherwise specified. dac resolution 16 - - bits dac differential nonlinearity - - 0.9 lsb total dynamic range tdr - 95 - db instantaneous dynamic range (olb = 1) (all outputs) idr 80 85 - db total harmonic distortion line out (note 5) - - 0.025 % (olb = 1) headphone out (note 6) thd - - 0.2 % speaker out (note 6) - - 0.32 % interchannel isolation line out (note 5) - 80 - db headphone out (note 6) - 40 - db interchannel gain mismatch line out - - 0.5 db headphone - - 0.5 db frequency response (note 1) (0 to 0.45 fs) -0.5 - +0.2 db programmable attenuation (all outputs) 0.2 - -94.7 db attenuation step size - 1.5 - db absolute attenuation step error - - 0.75 db offset voltage line out - 10 - mv full scale output voltage line output (note 5) 2.55 2.8 3.08 v pp with olb = 0 headphone output (note 6) 3.6 4.0 4.4 v pp speaker output-differential (note 6) 7.3 8.0 8.8 v pp full scale output voltage line output (note 5) 1.8 2.0 2.2 v pp with olb = 1 headphone output (note 6) 1.8 2.0 2.2 v pp speaker output-differential (note 6) 3.6 4.0 4.4 v pp gain drift - 100 - ppm/ c deviation from linear phase - - 1 degree out of band energy (22 khz to 100 khz) line out - -60 - db power supply power supply current (note 7) operating - 110 140 ma power down - 0.5 2 ma power supply rejection (1 khz) - 40 - db notes: 5. 10 k w , 100 pf load. headphone and speaker outputs disabled. 6. 48 w , 100 pf load. for the headphone outputs, thd with 10k w , 100pf load is 0.02%. 7. typically, 50% of the power supply current is supplied to the analog power pins (va1, va2) and 50% is supplied to the digital power pins (vd1, vd2). values given are for unloaded outputs. CS4215 ds76f2 3
digital characteristics (t a = 25 c; va1, va2, vd1, vd2 = 5v) parameter symbol min max units high-level input voltage v ih (vd1,vd2)-1.0 (vd1,vd2)+0.3 v low-level input voltage v il -0.3 1.0 v high-level output voltage at i 0 = -2.0 ma v oh (vd1,vd2)-0.2 - v low-level output voltage at i 0 = 2.0 ma v ol -0.1v input leakage current (digital inputs) - 10 m a output leakage current (high-z digital outputs) - 10 m a d/a interpolation filter characteristics parameter symbol min typ max units passband (fs is conversion freq.) 0 - 0.45fs hz frequency response -0.5 - +0.2 db passband ripple - - 0.1 db transition band 0.45fs - 0.55fs hz stop band 3 0.55fs - - hz stop band rejection 74 - - db group delay - 16/fs - s group delay variation vs. frequency - - 0.1/fs s a/d decimation filter characteristics parameter symbol min typ max units passband (fs is conversion freq.) 0 - 0.45fs hz frequency response -0.5 - +0.2 db passband ripple - - 0.1 db transition band 0.45fs - 0.55fs hz stop band 3 0.55fs - - hz stop band rejection 74 - - db group delay - 16/fs - s group delay variation vs. frequency - - 0.0 m s CS4215 4 ds76f2
sdin sdout t nz t pd1 t hz t pd1 t s1 t h1 ts 1, bit 7 ts 1, bit 7 ts 1, bit 6 sclk t pd1 t pd1 t pd2 tsout t pd2 ts 8, bit 0 ts 1, bit 6 fsync out tsin fsync in t s1 t h1 t h1 t s1 ts 8, bit 0 t sckl t sckh t sckw switching characteristics (t a = 25 c; va1, va2, vd1, vd2 = +5v, outputs loaded with 30 pf; input levels: logic 0 = 0v, logic 1 = vd1, vd2) parameter symbol min typ max units sclk period master mode, xclk = 1 (note 8) t sckw -1/(fs * bpf) - s slave mode (xclk = 0) tsckw 80 - - ns sclk high time slave mode, xclk = 0 (note 9) tsckh 25 - - ns sclk low time slave mode, xclk = 0 (note 9) tsckl 25 - - ns input setup time t s1 15 - - ns input hold time t h1 10 - - ns input transition time 10% to 90% points - - 10 ns output delay tpd1 - - 28 ns sclk to tsout tpd2 - - 30 ns output to hi-z state timeslot 8, bit 0 t hz - - 12 ns output to non-hi-z timeslot 1, bit 7 t nz 15 - - ns input clock frequency crystals - - 27 mhz clkin (note 10) 1.024 - 13.5 mhz input clock (clkin) low time 30 - - ns input clock (clkin) high time 30 - - ns sample rate fs 4 - 50 khz reset low time (note 11) 500 - - ns notes: 8. in master mode with bsel1,0 set to 64 or 128 bits per frame (bpf), the sclk duty cycle is 50%. when bsel1,0 is set to 256 bpf, sclk will have the same duty cycle as clkout. see internal clock generation section. 9. in slave mode, fsync and sclk must be derived from the master clock running the codec (clkin, xtal1, xtal2). 10. sample rate specifications must not be exceeded. 11. after powering up the CS4215, reset should be held low for 50 ms to allow the voltage reference to settle. CS4215 ds76f2 5
absolute maximum ratings (agnd, dgnd = 0v, all voltages with respect to 0v.) parameter symbol min max units power supplies: digital vd1,vd2 -0.3 6.0 v analog va1,va2 -0.3 6.0 v input current (except supply pins) - 10.0 ma analog input voltage -0.3 (va1, va2)+0.3 v digital input voltage -0.3 (vd1, vd2)+0.3 v ambient temperature (power applied) -55 +125 c storage temperature -65 +150 c warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd = 0v, all voltages with re- spect to 0v.) parameter symbol min typ max units power supplies: digital (note 8) vd1,vd2 4.75 5.0 5.25 v analog (note 8) va1,va2 4.75 5.0 5.25 v operating ambient temperature t a 02570 c note: 8. ? vd - va ? must be less than 0.5 volts (one diode drop). CS4215 6 ds76f2
note: agnd and dgnd pins must be on the same ground plane. 0.1 uf 1 uf 0.1 uf + 23 24 38 va1 va2 vd1 vd2 28 27 mout1 mout2 headr headl headc headphone jack 31 29 30 + > 1.0 uf 40 k + > 1.0 uf 40 k loutr loutl 33 32 vref 21 0.1 uf + 10 uf xtl2in xtl2out xtl1in xtl1out 40pf 40pf 40pf 40pf 10 11 6 7 22 25 2 9 1 uf + CS4215 minr minl linl linr agnd1 agnd2 dgnd1 dgnd2 pdn sdout sclk fsync tsout tsin d/c pio0 pio1 36 37 12 13 43 42 41 40 35 44 controller clkout 5 clkin 4 vd1 47k 18 16 microphone input right microphone input left +5v digital supply 1/2w 1/2w 12 w 12 w 600 w 600 w 0.0022 uf npo 0.0022 uf npo sdin 1 +5v 20k 20k 20k ferrite bead 16.9344 mhz 24.576 mhz reset > 32 w > 48 w +5v analog supply cmout 19 0.47 uf input buffers to o ptional refer to the analog inputs section for terminating unused line and mic inputs. all other unused inputs should be tied to gnd. all nc pins should be left floating. see line level inputs section 15 0.47 uf 150 0.01 uf npo 17 0.47 uf 150 0.01 uf npo figure 1. recommended connection diagram CS4215 ds76f2 7
functional description overview the CS4215 has two channels of 16-bit analog- to-digital conversion and two channels of 16-bit digital-to-analog conversion. both the adcs and the dacs are delta-sigma converters. the adc inputs have adjustable input gain, while the dac outputs have adjustable output attenuation. spe- cial features include a separate microphone input with a 20 db programmable gain block, an op- tional 8-bit m -law or a-law encoder/decoder, pins for two crystals to set alternative sample rates, direct headphone drive and mono speaker drive. control for the functions available on the CS4215, as well as the audio data, are communi- cated to the device over a serial interface. separate pins for input and output data are pro- vided, allowing concurrent writing to and reading from the device. data must be con- tinually written for proper operation. multiple CS4215 devices may be attached to the same data lines. analog inputs figure 1, the recommended connection diagram, shows examples of the external analog circuitry recommended around the CS4215. an internal multiplexer selects between line level inputs and microphone level inputs. input filters using a 150 w resistor and a .01 m f npo capacitor to ground are required to isolate the input op-amps from, and provide a charge re- serve for, the switched-capacitor input of the codec. the rc values may be safely changed by a factor of two. the hpf bit in control time slot 2 provides a high pass filter that will reduce dc offset on the analog inputs. using the high pass filter will cause slight distortions at very low frequencies. unused analog inputs that are not selected have a very high input impedance, so they may be tied to agnd directly. unused analog inputs that are selected should be tied to agnd through a 0.1uf capacitor. this prevents any dc current flow. line level inputs linl and linr are the line level input pins. these pins are internally biased to the cmout voltage. figure 2 shows a dual op-amp buffer which combines level shifting with a gain of 0.5 to attenuate the standard line level of 2 v rms to linr (pin 16) linl (pin 18) line in right line in left 0.01 uf npo 0.01 uf npo 150 150 0.47 uf 0.47 uf figure 3. ac coupled input. + _ 56 pf 10 k 20 k + _ 10 k 56 pf 5 k 20 k line in line in right left cmout linr linl op-amps are run from va1, va2 and agnd. 0.47 uf 0.47 uf 150 0.01 uf npo 0.47 uf 0.01 uf npo 150 0.47 uf (pin 16) (pin 18) (pin 19) example op-amps are lt1013 figure 2. dc coupled input. CS4215 8 ds76f2
1 v rms . the cmout reference level is used to level shift the signal. this level shifting allows the line inputs to be dc coupled into the CS4215. minimum adc offset results when the line inputs are dc coupled (see analog charac- teristics table). figure 3 shows an ac coupled input circuit for signals centered around 0 volts. the anti-alias- ing rc filter presents a low impedance at high frequencies and should be driven by a low im- pedance source. microphone level inputs internal amplifiers with a programmable 20 db gain block are provided for the microphone level inputs, minr and minl. figure 4 shows a sin- gle-ended input microphone pre-amplifier stage with a gain of 23 db. ac coupling is mandatory for these inputs since any dc offset on the input will be amplified by the codec. the 20 db gain block may be disabled using the mlb bit in control time slot 1. when dis- abled, the inputs become line level with full scale inputs of 1 vrms. adjustable input gain the signals from the microphone or the line in- puts are routed to a programmable gain circuit which provides up to 22.5 db of gain in 1.5 db steps. level changes only take effect on zero crossings to minimize audible artifacts, often re- ferred to as "zipper noise". the requested level change is forced if no zero crossing is found af- ter 511 frames (10.6 ms at a 48 khz frame rate). a separate zero crossing detector exists for each channel. analog outputs the analog outputs of the dacs are routed via an attenuator to a pair of line outputs, a pair of minr 1 uf c6 + c5 2 3 va+ 8 0.1 uf c4 560 pf 10 uf + r6 2.2 k r4 22.1 k 4 1 uf + r5 50 k minl 1 uf + c2 6 5 c1 560 pf r3 2.2 k r1 22.1 k 150 10 uf + r2 50 k npo npo c3 cmout c47 c8 1 7 r57 (mono) u2 mc33078 or c7 c46 mc33178 a =20 db 0.47 uf c48 0.01 uf npo 150 r56 0.01 uf npo microphone input left (pin 17) microphone input right (pin 15) 0.47 uf c45 figure 4. optional microphone input buffer CS4215 ds76f2 9
headphone outputs and a mono monitor speaker output. output level attenuator the dac outputs are routed through an attenu- ator, which provides 0 db to 94.5 db of attenuation, adjustable in 1.5 db steps. level changes are implemented using both analog and digital attenuation techniques. level changes only take effect on zero crossings to minimize audible artifacts. the requested level change is forced if an analog zero crossing does not occur within 511 frames (10.6 ms at a 48 khz frame rate). a separate zero crossing detector exists for each channel. line outputs loutr and loutl output an analog signal, centered around the cmout voltage. the mini- mum recommended load impedance is 8 k w . figure 1 shows the recommended 1.0 m f dc blocking capacitor with a 40 k w resistor to ground. when driving impedances greater than 10 k w , this provides a high pass corner of 20 hz. these outputs may be muted. headphone outputs headr and headl output an analog signal, centered around the headc voltage. the de- fault headphone output level (olb = 0) contains an optional 3 db gain over the line outputs which provides reasonable listening levels, even with small amplitude digital sources. these out- puts have increased current drive capability and can drive a load impedance as low as 48 w . ex- ternal 12 w series resistors reduce output level variations with different impedance headphones. the common return line from driving head- phones should be connected to headc, which is biased to the cmout voltage. this removes the need for ac coupling, and also controls where the return currents flow. all three head- phone output lines are short-circuit protected. these outputs may be muted. speaker output mout1 and mout2 differentially drive a small loudspeaker, whose impedance should be greater than 32 w . the signal is a summed version of the right and left line output, tapped off prior to the mute function, but after the attenuator. the speaker output may be independently muted. with olb = 0, the speaker output also contains a 3 db gain over the line outputs. when olb = 1, the speaker outputs are driven at the same level as the line outputs. some small speakers distort heavily when pre- sented with low frequency energy. a high-pass filter helps eliminate the low frequency energy and can be implemented by ac coupling both speaker terminals with a resistor to ground, on the speaker side of the dc blocking capacitors. the values selected would depend on the speaker chosen, but typical values would be 22 m f for the capacitors, with the positive side connected to the codec, and 50 k w resistors. this circuit is contained on the cdb4215 evaluation board as shown in the end of this data sheet. input monitor function to allow monitoring of the input audio signal, the output of the adcs can be routed through a monitor path attenuator, then digitally mixed into the input data for the dacs (see the front page block diagram). changes in the input gain or output level settings directly affect the monitor level. if full scale data from the adcs is added to full scale digital data from the serial interface, clipping will occur. calibration both output offset voltage and input offset error are minimized by an internal calibration cycle. at least one calibration cycle must be invoked CS4215 10 ds76f2
after power up. a calibration cycle will occur immediately after leaving the reset state. a cali- bration cycle will also occur immediately after going from control mode to data mode (d/ c go- ing high). when powering up the CS4215, or exiting the power down state, a minimum of 50 ms must occur, to allow the voltage reference to settle, before initiating a calibration cycle. this is achieved by holding reset low or stay- ing in control mode for 50 ms after power up or exiting power down mode. the input offset error will be calibrated for whichever input channel is selected (microphone or line, using the is bit). therefore, the is bit should remain steady while the codec is calibrating, although the other bits input to the codec are ignored. calibration takes 194 fsync cycles and sdout data bits will be zero during this period. the a/d invalid bit, adi (bit 7 in data time slot 6), will be high during calibration and will go low when calibration is finished. parallel input/output two pins are provided for parallel input/output. these pins are open drain outputs and require external pull-up resistors. writing a zero turns on the output transistor, pulling the pin to ground; writing a one turns off the output transistor, which allows an external resistor to pull the pin high. when used as an input, a one must be writ- ten to the pin, thereby allowing an external device to pull it low or leave it high. these pins can be read in control mode and their state is recorded in control register 5. these pins can be written to and read back in data mode using data register 7. figure 5 shows the parallel in- put/output timing. notes: 4. control mode read - the pio pins are sampled by a rising edge of sclk. 3. data mode read, write - are tied to the rising edge of fsync and clkout. they are independent of sclk. 2. control mode read - the data is sent out, via sdout, the same frame. 1. data mode read - the data is sent out via sdout on the next frame. data mode -read and write control mode - read only tsin sclk 1 sclk pio read pio read pio write 8.5 clkout's 11 clkout's sclk clkout fsync figure 5. pio pin timing CS4215 ds76f2 11
clock generation the master clock operating the CS4215 may be generated using the on-chip crystal oscillators, or by using an external clock source. in all data modes sclk and fsync must be synchronous to the selected master clock. if the master clock source stops, the digital fil- ters will power down after 5 m s to prevent overheating. if fsync stops, the digital filters will power down after approximately 1 fsync period. the CS4215 will not enter the total power down state. internal clock generation two external crystals may be attached to the xtl1in, xtl1out, xtl2in and xtl2out pins. use of an external crystal requires addi- tional 40 pf loading capacitors to digital ground (see figure 1). xtal1 oscillator is intended for use at 24.576 mhz and xtal2 oscillator is in- tended for use at 16.9344 mhz, although other frequencies may be used. the gain of the inter- nal inverter is slightly higher for xtal1, ensuring proper operation at >24 mhz frequen- cies. the crystals should be parallel resonant, fundamental mode and designed for 20 pf load- ing (equivalent to a 40 pf capacitor on each leg). if xtal1 or xtal2 is not selected as the mas- ter clock, that particular crystal oscillator is powered down to minimize interference. if a crystal is not needed, the xtl-in pin should be grounded. an example crystal supplier is cal crystal, telephone number (714) 991-1580. fsync and sclk must be synchronous to the master clock. when using the codec in slave mode with one of the crystals as master clock, the controller must derive fsync and sclk from the crystals, i.e. via clkout. note that clkout will stop in a low condition within two periods after d/ c goes low. an internally generated clock which is 256 times the sample rate (fsync rate) is output (clkout) for potential use with an external aes/ebu transmitter, or another CS4215. no glitch occurs on clkout when selecting alter- nate clock sources. clkout will stop in a low condition within two periods after d/ c goes low, assuming one of the crystal oscillators is se- lected, or either clkin or sclk is the master clock source and is continuous. the duty cycle of clkout is 50% if the master clock is one of the crystal oscillators and the dfr bits are 0, 1, 2, 6 or 7. if the dfr bits are 3 or 5, the duty cycle is 33% (high time). if the dfr bits are 4 then clkout has the timing shown in figure 6. if the master clock is sclk or clkin, the duty cycle of clkout will be the same as the mas- ter clock source. external clock an external clock input pin (clkin) is provided for potential use with an external aes/ebu re- ceiver, or an already existing system clock. when mck2 = 0, the input clock must be ex- actly 256 times the sample rate, and fsync and sclk must be synchronous to clkin. when mck2 = 1 the dfr bits allow various divide ratios off the clkin frequency. alternatively, an external high frequency clock may be driven into xtl1in or xtl2in. the correct clock source must be selected using the mck bits. manipulating dfr bits will allow various divide ratios from the clock to be se- 1 2 13 1/(128 x fsync) 1/(128 x fsync) 1 2 13 figure 6. clkout duty cycle using the on-chip crystal oscillator when dfr = 4 ( typically fsync = 37.8 khz) CS4215 12 ds76f2
lected. sclk and fsync must be synchronous to the external clock. as a third alternative, sclk may be pro- grammed to be the master clock input. in this case, it must be 256 times fs. serial interface the serial interface of the CS4215 transfers digi- tal audio data and control data into and out of the device. multiple CS4215 devices may share the same data lines. dsps supported include the motorola 56001 in network mode and a subset of the chi bus from at&t/intel. serial interface signals figure 7 shows an example of two CS4215 de- vices connected to a common controller. the serial data out (sdout) and serial data in (sdin) lines are time division multiplexed be- tween the CS4215s. the serial interface clock, sclk, is used for transmitting and receiving data. sclk can be generated by one of the CS4215s, or it can be input from an external sclk source. when gen- erated by an external source, sclk must be synchronous to the master clock. data is trans- mitted on the rising edge of sclk and is received on the falling edge of sclk. the sclk frequency is always equal to the bit rate. the frame synchronizing signal (fsync) is used to indicate the start of a frame. it may be output from one of the CS4215s, or it may be generated from an external controller. if fsync is generated externally, it must be high for at least 1 sclk period, and it must fall at least 2 sclks before the start of a new frame (see figure 8 ) . it must also be synchronous to the master clock. the frequency of fsync is equal to the system sample rate (see figure 8). each CS4215 requires 64 sclks to transfer all the data. the sclk frequency can be set to 64, 128, or 256 bits per frame, thereby allowing for 1, 2 or 4 CS4215s connected to the same bus. in a typical multi-part scenario, one CS4215 (the master) would generate fsync and sclk, while the other CS4215s (the slaves) would re- ceive fsync and sclk. the clkout of the master would be connected to the clkin of each slave device as shown in figure 7 . then, the master device would be programmed for the desired sample frequency (assuming one of the crystals is selected as the clock source), the num- ber of bits per frame, and for sclk and fsync to be outputs. the slave devices would be pro- grammed to use clkin as the clock source, the same number of bits per frame, and for sclk and fsync to be inputs. since clkout is al- controller sclk sdin sdout fsync sclk sdin sdout fsync tsin tsout pdn reset CS4215 d/c sclk sdin sdout fsync tsin tsout pdn reset CS4215 d/c d/c a b master slave clkin clkout xtl1in xtl1out xtl2in xtl2out figure 7. multiple CS4215s CS4215 ds76f2 13
fsync t1 tsn tsoutb ts1 ts2 ts3 ts2 ts7 ts8 ts8 ts1 tsouta tsinb device b device a ts8 tsina t1 1/frame rate or 1/system sample rate tsn time slot numbers figure 8. serial interface timing for 2 CS4215s sclk fsync data 1 2 8 9 16 17 18 64 65 66 67 6 1 ts1 ts2 7 610 65 76 1 10 7 0 7 0 ts3 ts8 68 ts1 tsin tsout 0 figure 9. frame sync and bit offset timing sclk 1 2 64 128 2 65 66 65 66 1 64 tsout b sdin sdout d/c _ control to a control to b control to a 3 4 67 68 3 4 fsync, tsin a tsout a, tsin b control mode control from a control from b 5 figure 10. control mode timing for 2 CS4215s CS4215 14 ds76f2
ways 256 times the sample frequency and scales with the selected sample frequency on the mas- ter, the slave devices will automatically scale with changes in the master codecs sample fre- quency. CS4215s are time division multiplexed onto the bus using the time slot out (tsout) and time slot in (tsin) signals. tsout is an output sig- nal that is high for one sclk bit time, and indicates that the CS4215 is about to release the bus. tsin is an input signal that informs the CS4215 that the next time slot is available for it to use. the first device in the chain uses fsync as its tsin signal. all subsequent devices use the tsout of the previous device as its tsin input. tsin must be high for at least 1 sclk period and fall at least 2 sclks before start of a new frame. serial interface operation the serial interface format has a variable number of time slots, depending on the number of CS4215s attached to the bus. all time slots have 8 bits. each CS4215 requires 8 time slots (64 bits) to communicate all data (see figure 9). control mode the control mode is used to set up the CS4215 for subsequent operation in data mode by load- ing the internal control registers. control mode is asserted by bringing d/ c low. if d/ c is low dur- ing power up, then the CS4215 will enter control mode immediately. the sclk and fsync pins are tri-stated, and the CS4215 will receive sclk and fsync from an external source. if the CS4215 is in master mode (sclk and fsync are outputs) and d/ c is brought low, then sclk & fsync will continue to be driven for a mini- mum of 4 and a maximum of 12 sclks, if the its bit = 0. if its is 1, sclk and fsync will three-state immediately after d/ c goes low. if d/ c is brought low when the codec is pro- grammed as master with its=0, the codec will timeout and release fsync and sclk within 100 m s. the values in the control registers for control of the serial ports are ignored in control mode. the data received on sdin is stored into the control registers which have addresses matching their time slots. the data in the regis- ters is transmitted on sdout with the time slot equal to the register number (see figure 10). the steps involved when going from data mode to control mode and back are shown in the flow chart in figure 11 . control formats the CS4215 control registers have the functions and time slot assignments shown in table 1 . the register address is the time slot number when d/ c is 0. reserved bits should be written as 0 and could be read back as 0 or 1. when compar- ing data read back, reserved bits should be masked. the sdout pin goes into a high-impedance state prior to time slot 1 and after time slot 8. the data listed below the reg- ister is its reset state. the parallel port register is used to read and write the two open-drain input/output pins. the outputs are all set to 1 on reset. pio bits are read only in control mode. note that, since pio signals are open drain signals, an external device time slot description 1 status 2 data format 3 serial port control 4test 5 parallel port 6 reserved 7 revision 8 reserved table 1. control registers CS4215 ds76f2 15
may drive them low even when they have been programmed as highs. therefore, the value read back may differ from the value written. in the data mode, (d/ c=1), this register can be read and written to through the serial port as part of the input settings registers. in control mode, (d/ c=0) these bits can only be read. CS4215 16 ds76f2
lower output level to maximum attenuation mute the speaker output set d/c low codec programmed for master mode & its=0? set external controller to drive sclk and fsync into the codec send valid control information with clb=0 read back and verify control information. mask off reserved bits n = 5 send valid control information with clb=0 n = n - 1 clb=0? set clb=1 and send at least two more frames of valid control information 2 set external controller to receive sclk and fsync from the codec is codec programmed for master mode? set d/c high. transmit/receive data with attenuated outputs and muted speaker for 194 fsync cycles while codec executes offset calibration transmit/receive audio data with desired level settings n = 0? poll for clb=0? 1 y n y n yy n n n y wait at least 12 sclk periods for fsync and sclk to three-state this is a software design choice, not a run-time conditional branch. 1 this will cause the codec to ignore any further bus activity. the sdout pin will be held in the high impedance state after transmitting 1 frame with clb=1 2 figure 11. control mode flow chart CS4215 ds76f2 17
bit name value function rsrv reserved bits must be written as 0. clb control latch bit 1 r ensures proper transition between control and data mode. olb output level bit 0 1 r line full scale outputs are 2.8 vpp (1vrms) headphone full scale output is 4.0 vpp. speaker full scale output is 8.0 vpp. line and headphone full scale outputs are 2.0 vpp. speaker full scale output is 4.0 vpp. mlb microphone level 0 1 r 20 db fixed gain enabled full scale microphone inputs are 0.288 vpp. 20 db fixed gain disabled full scale inputs are 2.88 vpp. control time slot 1, status register d7 d6 d5 d4 d3 d2 d1 d0 001mlbolbclbrsrv 001001xx register reset (r) control time slot 2, data format register d7 d6 d5 d4 d3 d2 d1 d0 hpf rsrv dfr2 dfr1 dfr0 st df1 df0 0x000001 register reset (r) bit name value function df1-0 data format selection 0 0 0 1 1 0 1 1 0 1 r 2 3 16-bit 2 s -complement linear. 8-bit m- law. 8-bit a-law. 8-bit unsigned linear. st stereo bit 0 1 r mono mode. stereo mode. dfr2-0 data conversion frequency selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 r 1 2 3 4 5 6 7 xtal1(khz) xtal2 (khz) clkin ( ? ) 24.576 mhz 16.9344 mhz 3072 8 5.5125 1536 16 11.025 896 27.42857 18.9 768 32 22.05 448 na 37.8 384 na 44.1 512 48 33.075 2560 9.6 6.615 rsrv reserved bit must be written as 0 hpf high pass filter 0 1 r disabled. enabled. a digital high pass filter is used to force the adc dc offset to zero. CS4215 18 ds76f2
bit name value function xen transmitter enable 0 1 r enable the serial data output. disable (high-impedance state) serial data output. xclk transmit clock 0 1 r receive sclk and fsync from external source slave mode generate sclk and fsync master mode bsel1-0 select bit rate 0 0 0 1 1 0 1 1 0 1 2 r 3 64 bits per frame. 128 bits per frame. 256 bits per frame. reserved. mck2-0 clock source select 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 r 1 2 3 4 sclk is master clock, 256 bits per frame. bsel must equal 2, and xclk must equal 0. xtal1, 24.576 mhz, is clock source. xtal2, 16.9344 mhz, is clock source. clkin is clock source, and must be 256xfs. clkin is clock source, dfr2-0 select sample frequency. its immediate three- state 0 1 r sclk and fsync three-state up to 12 clocks after d/ c goes low. sclk and fsync three-state immediately after d/ c goes low. control time slot 3, serial port control register d7 d6 d5 d4 d3 d2 d1 d0 its mck2 mck1 mck0 bsel1 bsel0 xclk xen 00001001 register reset (r) control time slot 4, test register d7 d6 d5 d4 d3 d2 d1 d0 test enl dad 00000000 register reset (r) bit name value function dad loopback mode 0 1 r digital-digital loopback. digital-analog-digital loopback. enl enable loopback te s t i n g 0 1 r disable. enable. test test bits the test bits must be written as zero, otherwise special factory test modes may be invoked. CS4215 ds76f2 19
control time slot 5, parallel port register d7 d6 d5 d4 d3 d2 d1 d0 pio1 pio0 rsrv 11xxxxxx register reset (r) bit name value function rsrv reserved bits must be written as 0. pio1-0 parallel i/o bits 1 1 3 r see the parallel input/output section. control time slot 6, reserved register d7 d6 d5 d4 d3 d2 d1 d0 rsrv xxxxxxxx register reset (r) control time slot 7, version register d7 d6 d5 d4 d3 d2 d1 d0 rsrv ver3 ver2 ver1 ver0 xxxx0010 register reset (r) bit name value function ver3-0 device version number 0 0 0 0 0 0 0 1 0 0 1 0 0 1 2 r "c". see appendix a. "d". see appendix a. "e". this data sheet rsrv reserved bits must be written as 0. bit name value function rsrv reserved bits must be written as 0. control time slot 8, reserved register d7 d6 d5 d4 d3 d2 d1 d0 rsrv xxxxxxxx register reset (r) bit name value function rsrv reserved bits must be written as 0. CS4215 20 ds76f2
data mode the data mode is used during conversions to pass digital data between the CS4215 and exter- nal devices. the frame sync rate is equal to the value of the conversion frequency set by the dfr2-dfr0 bits of the data format register. each frame has either 64, 128, or 256 bit times depending on the bsel bits in the serial con- trol register. control of gain, attenuation, input selection and output muting are embedded in the data stream. data formats all time slots contain 8 bits. the msb of the data is transmitted/received first. the CS4215 data registers have the functions and time slot as- signments shown in table 2. the register address is the time slot number when d/ c is 1. the sdout pin goes into a high-impedance state prior to time slot 1 and after time slot 8 (see figure 12). the CS4215 supports four audio data formats: 16-bit 2s-complement linear, 8-bit unsigned lin- ear, 8-bit a-law, and 8-bit m -law. figure 13 illustrates the transfer characteristic for 16-bit and 8-bit linear formats. note that a digital code sclk 12 64 128 2 65 66 1 tsout b sdin d/c _ data to a data to b data to a 3 4 67 68 34 fsync, tsin a tsout a, tsin b 128 69 data from a data from b data from a sdout data mode figure 12. data mode timing for 2 CS4215s 0 +fs -fs analog value 0 65 128 191 255 digital code 8-bit unsigned: 16-bit 2s comp: -32768 -16384 0 16384 32767 figure 13. linear data formats time slot description 1 2 3 4 5 6 7 8 left audio ms8 bits left audio ls8 bits right audio ms8 bits right audio ls8 bits output setting output setting input setting input setting table 2. data registers CS4215 ds76f2 21
of 128 (80 hex) is considered analog zero for the 8-bit unsigned format. a non-linear coding scheme is used for the com- panded formats as shown in figure 14 . this scheme is compatible with ccitt g.711. com- panding uses more precision at lower amplitudes at the expense of less precision at higher ampli- tudes. m -law is equivalent to 13 bits at low signal levels and a-law is equivalent to 12 bits. this low-level dynamic range is obtained at the expense of large-signal dynamic range which, for both m -law and a-law, is equivalent to 6 bits. the CS4215 internally operates at 16 bits. the companded data is expanded to the upper 13 (12) bits for the dacs and compressed from the upper 13 (12) bits to 8 bits for the adcs. data time slot 1&2, left channel audio data time slot 1 and 2 contain audio data for the left channel. in mono modes, only the left channel data is used, however both the right and left output dacs are driven. in 8-bit modes, only time slot 1 is used for the data. data time slot 3&4, right channel audio data time slot 3 and 4 contains audio data for the right channel. in mono modes, the right adc outputs zero and the right dac uses the left digital data. in 8-bit modes, only time slot 3 is used for the data. figure 15 summarizes all the time slot bit alloca- tions for the 4 data modes and for control mode. reset reset going low causes all the internal control registers to be set to the states shown with each register description. reset must be brought low and high at least once after power up. reset returning high causes the CS4215 to execute an offset calibration cycle. reset or d/ c returning high should occur at least 50 ms after the power supply has stabilized to allow the voltage refer- ence to settle. data time slot 5, output setting d7 d6 d5 d4 d3 d2 d1 d0 he le lo5 lo4 lo3 lo2 lo1 lo0 00111111 register reset (r) bit name value function lo5-0 left channel output attenuation setting 1 1 1 1 1 1 63 r 1.5db attenuation steps. lo5 is the msb. 0 = no attenuation. 111111 = -94.5db le line output enable 0 1 r analog line outputs off (muted). analog line outputs on. he headphone output enable 0 1 r headphone output off (muted). headphone output on. 0 +fs -fs digital code analog value a-law: 2ah 15h 95h aah 7fh/ffh 55h/d5h 00h 3fh bfh 80h u-law: figure 14. companded data formats CS4215 22 ds76f2
data time slot 8, input setting d7 d6 d5 d4 d3 d2 d1 d0 ma3 ma2 ma1 ma0 rg3 rg2 rg1 rg0 11110000 register reset (r) bit name value function rg3-0 right channel input gain setting 0 0 0 0 r 1.5db gain steps. rg3 is the msb. 0 = no gain, 1111 = 22.5db gain. ma3-0 monitor path attenuation 1 1 1 1 15 r 6db attenuation steps. ma3 is the msb. 0 = no attenuation, 1111 = mute. bit name value function lg3-0 left channel input gain setting 0 0 0 0 r 1.5db gain steps. lg3 is the msb. 0 = no gain, 1111 = 22.5db gain. is input select 0 1 r line level inputs (linl, linr). microphone level inputs (minl, minr). ovr overrange 0 r when read as 1, this bit indicates that an input over- range condition has occurred. the bit remains set until cleared by writing 0 into the register. writing a 1 enables the overrange detection. the bit will remain 0 until an over-range occurs. serial port clear has priority over internal settings. pio1-0 parallel i/o 1 1 3 r parallel input/output bits. data time slot 7, input setting d7 d6 d5 d4 d3 d2 d1 d0 pio1 pio0 ovr is lg3 lg2 lg1 lg0 11000000 register reset (r) data time slot 6, output setting d7 d6 d5 d4 d3 d2 d1 d0 adi se ro5 ro4 ro3 ro2 ro1 ro0 10111111 register reset (r) bit name value function ro5-0 right channel output attenuation setting 1 1 1 1 1 1 63 r 1.5db attenuation steps. ro5 is the msb. 0 = no attenuation. 111111 = -94.5db not used in mono modes. se speaker enable 0 1 r speaker off (muted). speaker on. adi a/d data invalid 0 1 r a/d data valid. a/d data invalid. busy in calibration. CS4215 ds76f2 23
lsb msb msb msb msb lsb lsb lsb lsb msb msb lsb 16 bit stereo right channel audio lo ro ovr is lg pio rg lo ro ovr is lg pio 12345 678 16 bit mono left right lo ro ovr is lg pio rg 8 bit stereo lo ro ovr is lg pio 8 bit mono control mode left st df mck bsel dad enl pio version dfr ma ma ma ma left channel audio left channel audio se se se se he le he le he le he le its clb olb test xen xclk adi adi adi adi hpf mlb 001 figure 1 5. time slot/register overview CS4215 24 ds76f2
power down mode bringing the pdn pin high puts the CS4215 into the power down mode. in this mode headc and cmout will not supply current. power down will change all the control registers to the reset state shown under each control time slot register. in the power down mode, the tsout pin will follow the tsin state with less than 10 ns delay. after returning to normal operation from power down, an offset calibration cycle must be exe- cuted. either bringing reset low then high, or updating the control registers, will cause an off- set calibration cycle. in either case, a delay of 50 ms must occur after pdn goes low before executing the offset calibration. this allows the internal voltage reference time to settle. loopback test modes the CS4215 contains three loopback modes that may be used to test the codec. two of the loop- back test modes are designed to allow the host to perform a self-test on the CS4215. the third mode allows laboratory testing using external equipment. host self-test loopback modes since the CS4215 is a mixed-signal device, it is equipped with an internal register that will en- able the host to perform a two-tiered test on power-up or as needed. the loopback test is en- abled by setting the enable loopback bit, enl, in control register 4. the first tier of loopback is a digital-digital loopback, dd, which is selected by clearing the dad bit in control register 4 (see sdout a/ m decode digital- analog- digital loopback gain attenuation d/a a/d digital-d igital loopback sdin lout rout lin rin dad dd CS4215 sdout a/ m decode gain attenuation d/a a/d a/ m encode sdin lout rout lin rin CS4215 monitor = 0 ada monitor = 1111 (full mute) (still operate) (disconnected) (d ac data = 0) 0 is different for each data format a/ m encode figure 16. dd, dad & ada loopback paths CS4215 ds76f2 25
figure 16). dd loopback checks the interface between the host and the CS4215 by taking the data on sdin and looping it back onto sdout, with the data on sdout being one frame de- layed from the data on sdin. the host can verify that the data received is exactly the same as the data sent, thereby indicating the interface between the two devices and the digital interface on the CS4215 are operating properly. the out- put dacs are functional in dd loopback. now that the interface has been verified, the rest of the CS4215 can be tested using the second tier of loopback. the second tier of loopback is a digital-analog- digital loopback, dad, which is selected by setting the dad bit in control register 4. dad loopback checks the analog section of the CS4215 by connecting the right and left analog outputs, after the output attenuator, to the analog inputs of the gain stage. this allows testing of most of the CS4215 from the host by sending a known digital signal to the dacs and monitoring the digital signal from the adcs. during dad loopback, the monitor attenuator must be set at maximum (full mute), and the analog outputs may be individually muted. the analog inputs are disconnected internally. the flow of test data for both dd and dad loopback modes is illus- trated in the top portion of figure 16. analog-to-analog loopback mode a third loopback mode is achieved by setting the monitor attenuator to zero attenuation and send- ing the dacs digital zero via sdin. this loopback is termed analog-digital-analog, ada, since the selected analog input will now appear on the enabled analog outputs. since this test is controlled by external stimulus and the host is not involved (except to send the dacs zeros), it is generally considered a laboratory test as op- posed to a self test. the bottom portion of figure 16 illustrates the ada signal flow through the CS4215. note that this test requires the host send analog zeros to the dac. each data format has a different code for zero. see figures 13 and 14. 0.1 uf 2.0 1 uf 0.1 uf + 23 24 38 va1 va2 vd1 vd2 1 uf + CS4215 +5v supply ferrite bead 1 uf 0.1 uf + figure 17. optional power supply arrangement CS4215 26 ds76f2
power supply and grounding when using separate supplies, the digital power should be connected to the CS4215 via a ferrite bead, positioned closer than 1" to the device (see figure 1). the codec va1, va2 pins should be derived from the cleanest power source available. if only one supply is available, use the suggested arrangement in figure 17. va1 supplies analog power to the adcs and dacs while va2 sup- plies power to the output power drivers (headphones and speaker). the large currents necessary for va2 are not flowing through the 2.0 w resistor, and therefore do not corrupt the va1 converter supply. the CS4215 along with associated analog cir- cuitry, should be positioned near to the edge of the circuit board, and have its own, separate, ground plane. on the CS4215, the analog and digital grounds are internally connected; there- fore, the four ground pins must be externally connected with zero impedance between ground pins. the best solution is to place the entire chip on a solid ground plane as shown in figure 18. preferably, it should also have its own power plane. a single connection between the CS4215 ground and the board ground should be posi- tioned as shown in figure 18 . figure 19 illustrates the optimum ground and de- coupling layout for the CS4215 assuming a surface-mount socket and leaded decoupling ca- pacitors. surface-mount sockets are useful since the pad locations are exactly the same as the ac- tual chip; therefore, given that space for the socket is left on the board, the socket can be op- tional for production. figure 19 depicts the top layer containing signal traces and assumes the bottom or inter-layer contains a solid analog ground plane. the important points with regards to this diagram are that the ground plane is solid under the codec and connects all codec ground pins with thick traces providing the abso- lute lowest impedance between ground pins. the decoupling capacitors are placed as close as pos- sible to the device which, in this case, is the socket boundary. the lowest value capacitor is digital ground plane note that the CS4215 is oriented with its digital pins towards the digital end of the board. cpu & digital logic codec digital signals codec analog signals & components analog ground plane 1/8" > > CS4215 +5v ferrite bead ground connection figure 18. suggested layout guideline CS4215 ds76f2 27
1 0.1 uf 10 uf 1 uf 0.1 uf 0.1 uf + + analog supply 1 uf + digital supply figure 20. CS4215 surface mount decoupling layout 1 0.1 uf 10 uf 1 uf 0.1 uf 0.1 uf + + analog supply digital supply 1 uf + figure 19. CS4215 decoupling layout guideline CS4215 28 ds76f2
placed closest to the codec. vias are placed near the agnd and dgnd pins, under the ic, and should be attached to the solid analog ground plane on another layer. the negative side of the decoupling capacitors should also attach to the same solid ground plane. traces bringing the power to the codec should be wide thereby keep- ing the impedance low. although not shown in the figures, the trace lay- ers (top layer in the figures) should have ground plane fill in-between the traces to minimize cou- pling into the analog section. see the cdb4215 evaluation board data sheet for an example lay- out. if using all surface-mount components, the de- coupling capacitors should still be placed on the layer with the codec and in the positions shown in figure 20. the vias shown are assumed to at- tach to the appropriate power and analog ground layers. traces bringing power to the codec should be as wide as possible to keep the imped- ance low. for the same reason, vias should be large for power and ground runs. if using through-hole sockets, effort should be made to find a socket with the minimum height which will minimize the socket impedance. when using a through-hole socket, the vias un- der the codec in figure 19 are not needed since the pins serve the same function. adc and dac filter response plots figures 21 through 27 show the overall fre- quency response, passband ripple and transition band for the CS4215 adcs and dacs. fig- ure 27 shows the dacs deviation from linear phase. fs is the selected sample frequency. since the sample frequency is programmable, the fil- ters will adjust to the selected sample frequency. fs is also the fsync frequency. -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 magnitude (db) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 input frequency (fs) figure 21. adc frequency response 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 input frequency (fs) -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.0 0.1 0.2 magnitude (db) figure 22. adc passband ripple -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 magnitude (db) 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 input frequency (fs) figure 23. adc transition band CS4215 ds76f2 29
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 input frequency (fs) -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.0 0.1 0.2 magnitude (db) figure 25. dac passband ripple -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 magnitude (db) 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 input frequency (fs) figure 26. dac transition band 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 input frequency (fs) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 phase (degrees) figure 27. dac deviation from linear phase 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 input frequency (fs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 magnitude (db) figure 24. dac frequency response CS4215 30 ds76f2
pin descriptions note: all unlabeled pins are no connects 75 76 100 77 79 81 83 85 87 89 91 93 95 97 tsin tsout fsync sclk sdout sdin dgnd1 vd1 clkin clkout xtl1in mout1 mout2 agnd2 va2 va1 agnd1 vref cmout 26 50 45 43 41 39 37 35 33 31 xtl1out vd2 dgnd2 xtl2in xtl2out reset pdn minr linr minl linl 1 25 2 4 6 8 10 14 16 18 20 22 24 51 52 74 72 70 66 64 60 56 pio1 pio0 d/c loutr loutl headl headc headr CS4215 100-pin tqfp (q) top view CS4215 ds76f2 31
power supply va1, va2 - analog power input, pins 23(l), 24(l), 37(q), 39 (q) +5 v analog supply. agnd1, agnd2 - analog ground, pins 22(l), 25(l), 35(q), 41(q) analog ground. must be connected to dgnd1, dgnd2 with zero impedance. vd1, vd2 - digital power input, pins 3(l), 8(l), 91(q), 4(q) + 5 v digital supply. dgnd1, dgnd2 - digital ground, pin 2(l), 9(l), 89(q), 6(q) digital ground. must be connected to agnd1, agnd2 with zero impedance. CS4215 44-pin plcc (l) top view 18 20 22 24 26 28 1 2 4 640 42 44 12 8 10 14 16 7 9 11 13 15 17 29 31 33 35 37 39 34 30 32 36 38 sdin dgnd1 sdout vd1 sclk clkin fsync clkout tsout xtl1in tsin xtl1out nc vd2 nc dgnd2 pio1 xtl2in pio0 xtl2out d/ c reset nc pdn loutr nc loutl minr headl linr headc minl headr linl mout1 cmout mout2 nc nc vref agnd2 agnd1 va2 va1 CS4215 32 ds76f2
analog inputs linl, linr - left and right channel line level inputs, pins 18(l), 16(l), 24(q), 20(q) line level input connections for the right and left channels. minl, minr - left and right channel microphone inputs, pins 17(l), 15(l), 22(q), 18(q) microphone level input connections for the right and left channels. analog outputs loutr, loutl - line level outputs, pins 33(l), 32(l), 66(q), 64(q) one pair of line level outputs are provided. the output level for right and left outputs can be independently varied. these outputs can be muted. headr, headl - headphone outputs, pins 29(l), 31(l), 52(q), 60(q) headr and headl are intended to drive a pair of headphones. additional current drive, along with an optional +3 db of gain, ensures reasonable listening levels. these outputs can be muted. headc - common return for headphone outputs, pin 30(l), 56(q) headc is the return path for large currents when driving headphones from the headr and headl outputs. this pin is nominally at 2.1 v. cmout - common mode output, pin 19(l), 31(q) common mode voltage output. this signal may be used for level shifting the analog inputs. the load on cmout must be dc only, with an impedance of not less than 10k w . cmout should be bypassed with a 0.47 m f to agnd. cmout is nominally at +2.1v. mout1, mout2 - mono speaker outputs, pins 28(l), 27(l), 45(q), 43(q) mono external loudspeaker differential output connections. the loudspeaker output is a mix of left and right line outputs. independent muting of the speaker is provided. mout1 and mout2 output voltage is nominally at 2.1 v with no signal. vref - voltage reference output, pin 21(l), 33(q) the on-chip generated adc/dac reference voltage is brought out to this pin for decoupling purposes. this output must be bypassed with a 10 m f capacitor in parallel with a 0.1 m f capacitor to the adjacent agnd1 pin. no other external load may be connected to this output. digital interface signals sdin - serial data input, pin 1(l), 87(q) audio data for the dacs and control information for all functions is presented to the CS4215 on this pin. sdout - serial data output, pin 44(l), 85(q) audio data from the adcs and status information concerning all functions is written out by the CS4215 onto this pin. CS4215 ds76f2 33
sclk - serial port clock, pin 43(l), 83(q) sclk rising causes the data on sdout to be updated. sclk falling latches the data on sdin into the CS4215. the sclk signal can be generated off-chip, and input into the CS4215. alternatively, the CS4215 can generate and output sclk in data mode. fsync - frame sync signal, pin 42(l), 81(q) the frame synchronizing signal is sampled by sclk, with a rising edge indicating a new frame is about to start. fsync frequency is always the system sample rate. each frame may have 64, 128 or 256 data bits, allowing for 1, 2 or 4 CS4215s connected to the same bus. fsync may be input to the CS4215, or may be generated and output by the CS4215 in data mode. when fsync is an input, it must be high for at least 1 sclk period. fsync can stay high for the rest of the frame, but must return low at least 2 sclks before the next frame starts. tsin - time slot input, pin 40(l), 77(q) tsin high for at least 1 sclk cycle indicates to the CS4215 that the next time slot is allocated for it to use. tsin is normally connected to the tsout pin of the previous device in the chain. tsin should be connected to fsync for the 1st (or only) CS4215 in the chain. tsout - time slot output, pin 41(l), 79(q) tsout goes high for 1 sclk cycle, indicating that the CS4215 is about to release the data bus. normally connected to the tsin pin on the next device in the chain. d/ c - data/control select input, pin 35(l), 70(q) when d/ c is low, the information on sdin and sdout is control information. when d/ c is high, the information on sdin and sdout is data information. pdn - power down input, pin 13(l), 16(q) when high, the pdn pin puts the CS4215 into the power down mode. in this mode headc and cmout will not supply current. power down causes all the control registers to change to the default reset state. in the power down mode, the tsout pin remains active, and follows tsin delayed by less than 10 ns. reset - active low reset input, pin 12(l), 14(q) upon reset, the values of the control information (when d/ c = 0) will be initialized to the values given in the reset description section of this data sheet. clock and crystal pins xtl1in, xtl1out, xtl2in, xtl2out - crystals 1 and 2 inputs and outputs, pins 6(l), 7(l), 10(l), 11(l), 97(q), 2(q), 8(q), 10(q) input and output connections for crystals 1 and 2. one of these oscillators may provide the master clock to run the CS4215. clkin - external clock input, pin 4(l), 93(q) external clock input optionally used to clock the CS4215. the clkin frequency must be 256 times the maximum sample rate (fsync frequency). CS4215 34 ds76f2
clkout - master clock output, pin 5(l), 95(q) master clock output, whose frequency is always 256 times the system sample rate (fsync frequency). clkout is active only in data mode and is low during control mode. miscellaneous pins pio0, pio1 - parallel input/output, pins 36(l), 37(l), 72(q), 74(q) these pins are provided as general purpose digital parallel input/output and have open drain outputs. an external pull-up resistor is required. they can be read in control mode, and read and written to in data mode. note: all unlabeled pins are no connects which should be left floating. CS4215 ds76f2 35
parameter definitions resolution the number of bits in the input words to the dacs, and in the output words in the adcs. differential nonlinearity the worst case deviation from the ideal codewidth. units in lsb. total dynamic range the rms value of a full scale signal to the lowest obtainable noise floor. it is measured by comparing a full scale signal to the lowest noise floor possible in the codec (ie. attenuation bits for the dacs at full attenuation.) units in db. instantaneous dynamic range the dynamic range available at any instant in time. it is measured using s/(n+d) with a 1 khz, -60 db input signal, with 60 db added to compensate for the small input signal. use of a small input signal reduces to harmonic distortion components of the noise to insignificance. units in db. total harmonic distortion thd is the ratio of the rms value of a signals first five harmonic components to the rms value of the signals fundamental component. thd is calculated for the adcs using an input signal which is 3db below typical full-scale, and is referenced to typical full-scale. a digital full-scale output is used to calculate thd for the dacs. interchannel isolation the amount of 1 khz signal present on the output of the grounded input channel with 1 khz 0 db signal present on the other channel. units in db. interchannel gain mismatch for the adcs, the difference in input voltage that generates the full scale code for each channel. for the dacs, the difference in output voltages for each channel with a full scale digital input. units in db. frequency response worst case variation in output signal level versus frequency over 10 hz to 20 khz. units in db. step size typical delta between two adjacent gain or attenuation values. units in db. absolute step error the deviation of a gain or attenuation step from a straight line passing through the no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). units in db. CS4215 36 ds76f2
out-of-band energy the ratio of the rms sum of the energy from 0.46xfs to 2.1xfs compared to the rms full-scale signal value. tested with 48khz fs giving an out-of-band energy range of 22khz to 100khz. offset error for the adcs, the deviation in lsbs of the output from mid-scale with the selected input at cmout. for the dacs, the deviation of the output from cmout with mid-scale input code. units in volts. CS4215 ds76f2 37
appendix a this data sheet describes version 2 of the CS4215. therefore, this appendix is included to describe the differences between versions 0,1 and version 2. this information is only useful for users that still have version 0 and version 1 devices since version 2 devices will supplant the earlier versions. the version number can be found in control mode, time slot 7. the version can also be identified by the revision letter stamped on the top of the actual chip. the revision letter immediately precedes the data code on the second line of the package marking (see general information section of the crystal data book). version 0 corresponds to chip revision c, version 1 corresponds to chip revision d, and version 2 cor- responds to chip revision e. future chip revisions (ie. f, g, h) may still be version 2 since the version number only changes if there is a register change to the part that will affect driver software. the functional differences between version 0(rev. c) and version 1(rev. d) 1. fsync on version 0 must be only one sclk period high, whereas on version 1 fsync must be at least one sclk period high. 2. when driving an external cmos clock into one of the xtl-in pins, version 0 devices must have a series resistor of at least 1k w between the CS4215 and the clock source. the resistor is needed be- cause the codec will put xtl-in to ground (on version 0 only) when that crystal is not selected, as is the case on power-up. in version 1 the xtl-in pins are floated when not selected; therefore, the series resistor is not needed on version 1. version 1 will work properly if the resistor is included. 3. the olb and its bits do not exist on version 0. writing these bits as zero makes both versions function identically; therefore, version 1 is backwards compatible with version 0. 4. when entering control mode, clkout stops 4 to 12 clocks later and may start up briefly when switching master clock sources on version 0. on version 1 clkout stops within two clocks and doesnt start up until data mode is entered. 5. in version 0 the headphone and speaker outputs are not short-circuit protected, whereas in version 1 they are short-circuited protected. the functional differences between version 1(rev. d) and version 2(rev. e) 1. the mlb, hpf, and mck2 bits in control mode do not exist in version 0 or version 1. writing these bits as zero makes all versions functionally identical; therefore, version 2 is backwards compat- ible with previous versions. 2. the a/d invalid bit, adi, in data mode does not exist in version 0 or version 1. 3. the 8-bit unsigned data format (df1,0=3) does not exist in version 0 or version 1. 4. sdout contained random data during calibration in versions 0 and 1. sdout outputs zeros dur- ing calibration in version 2. CS4215 38 ds76f2
features easy dsp hook-up correct grounding and layout microphone pre-amplifier line input buffer digital patch area general description the cdb4215 evaluation board allows easy evaluation of the CS4215 audio multimedia codec. analog inputs provided include two 1 / 4 " microphone jacks and two bnc line inputs. analog outputs provided are two bnc line outputs, one stereo 1 / 4 " headphone jack and one pair of speaker terminals. digital interfacing is facilitated by two buffered ribbon cable headers. one contains the serial port and the other contains the codec control pins. ordering information: cdb4215 jul 93 ds76db3 39 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445 7222 fax: (512) 445 7581 CS4215 evaluation board semiconductor corporation cdb4215 copyright ? crystal semiconductor corporation 1992 (all rights reserved) CS4215 +5va digital i/o buffers pio indicators digital patch area line inputs microphone jacks line outputs headphone jack speaker terminals clkout agnd +5vd dgnd clkin a = 23 db a = - 6 db serial port header control pin header
general information the cdb4215 is designed to provide an easy platform for evaluating the performance of the CS4215 multimedia audio codec. the board provides a buffered serial interface for easy con- nection to the serial port of a dsp or other serial device. a single +5 v power supply is all that is required to power the evaluation board. the line input buffers are designed to accept standard cd-level inputs of 2 v rms and bnc- to-phono adapters are included to support various test setups. the microphone inputs con- sist of two 1 / 4 " mono jacks that are designed to accept standard single-ended dynamic or con- denser microphones. the line outputs are supplied via bnc jacks with two more bnc-to-phono adapters. the headphone output is supplied via a 1 / 4 " stereo jack and will drive headphones of 48 w or greater. this includes most "walkman" style headphones. speaker terminals are provided and can be connected to speakers with an impedance of 32 w or greater. the film plots of the board are included to pro- vide an example of the optimum layout, grounding, and decoupling arrangement for the CS4215. power supply circuitry figure 1 illustrates a portion of the cdb4215 schematic and includes the CS4215 codec along with power supply circuitry. power is supplied to the board via two sets of binding posts, one for digital and one for analog. the analog supply must be +5 volts and supplies power for the en- tire codec (both digital and analog power supply pins) along with the analog input buffers for the line and microphone inputs. the digital supply is also +5 volts and supplies power to the digital header buffer circuitry. space for a ferrite bead inductor, l1, has been provided so that the board may be modified to power the codec from the digital supply. selection of l1 will depend on the characteristics of the noise on the digital sup- ply used. analog inputs the analog inputs consist of a pair of 1 / 4 " jacks for two microphones, and a pair of bncs for line level inputs. bnc-to-phono adapters are in- cluded to allow testing of the line inputs using coax or standard audio cables. the line-level inputs go through a buffer, fig- ure 2, with a gain of 0.5 which allows input signals of up to 2 v rms . the two microphone inputs are single-ended and are designed to work with both condenser and dynamic mics. the microphone input buffer cir- cuit, shown in figure 3, has a gain of 23 db thereby defining a full-scale input voltage to the mic jacks of 19.5 mvpp. analog outputs the cdb4215 includes three analog output paths: a pair of line output bncs, a stereo 1 / 4 " headphone jack, and a pair of mono speaker ter- minals. the CS4215 drives the line outputs into an r-c filter and then to a pair of bncs. as with the line inputs, bnc-to-phono adapters are provided for flexibility. the line outputs can drive an im- pedance of 10 k w or more, which is the typical input impedance of most audio gear. the stereo headphone output can drive head- phones with an impedance of 48 w or greater. this includes most "walkman" style headphones. cdb4215 40 ds76db3
va1 va2 vd1 vd2 28 27 mout1 mout2 headr headl headc headphones 31 29 30 39 k 39 k loutr loutl 33 32 22 25 2 agnd1 agnd2 dgnd1 1/2w 1/2w 16 16 600 600 0.0022 uf npo 0.0022 uf npo CS4215 u1 xtl2out xtl2in xtl1in xtl1out 40pf 40pf 40pf 40pf 10 11 6 7 16.9344 mhz 24.576 mhz c22 c23 c24 c25 clkin 4 9 dgnd2 22 uf + r51 50 k r52 50 k c34 22 uf + mout1 mout2 r21 r20 1 uf 1 uf c29 c28 r24 r25 c27 c26 loutr loutl r26 r27 minr minl linr cmout linl 15 17 16 19 18 microphone input buffer see figure 3 line input buffer see figure 2 y2 y1 c16 0.1 uf c21 c20 21 vref 0.1 uf 1 uf 0.1 uf + 23 24 38 1 uf + ferrite bead 0.1 uf 47 uf + c32 c30 +5va +5vd c11 c12 c13 c14 0.1 uf 47 uf + c33 c31 r28 d1 p6ke d2 p6ke l1 va 2 dgnd agnd vd 10 uf + see fig 5 + + figure 1. CS4215 & power supplies cdb4215 ds76db3 41
minr 1 uf c6 + c5 2 3 va+ 8 c4 560 pf npo 10 uf + r6 1.5 k r4 22.1 k 4 150 0.47 uf 15 1 uf + r5 50 k minl (mono) 1 uf + c2 6 5 c1 560 pf r3 1.5 k r1 22.1 k 150 0.47 uf 17 10 uf + r2 50 k npo 0.01 uf npo c3 npo 0.01 uf minr cmout minl 19 CS4215 c48 c47 r56 c8 0.1 uf 1 7 r57 u2 mc33178 c7 c45 c46 figure 3. microphone input buffer + _ 56 pf npo 10 k 20 k + _ 10 k 56 pf npo 5 k 20 k cmout linr linl 0.47 uf 150 1 uf 0.01 uf npo 150 16 18 19 c17 c35 + c18 r18 r15 c19 r19 va r14 r17 1 2 3 4 8 u3 5 6 0.47 uf c37 7 r12 r13 linr linl 0.01 uf npo c10 c36 0.1 uf c9 lt1013 CS4215 (mono) figure 2. line input buffer cdb4215 42 ds76db3
speaker terminals are provided and are labeled mout1 and mout2. speakers connected to the terminals must have an impedance of 32 w or greater. dc blocking capacitors are included to form a high-pass filter with the speaker imped- ance. this filter blocks very low frequency signals which can heavily distort some inexpen- sive speakers. serial interface the cdb4215 is primarily designed to evaluate the CS4215 is single chip mode, i.e. only one codec on the serial bus. this is the default state for the cdb4215 and is defined by having the p4 jumper in the "1chip" position, see figure 4, which connects fsync to tsin. this connec- tion defines the board codecs time slots as the first 64 bits of the frame. the only signals that need to be connected to the dsp are the five sig- nals on header j15. the serial interface is illustrated in figure 4. if the goal is to connect multiple cdb4215s on the same serial port, jumper p4 must be in the "multi" position which disconnects tsin from fsync. the multi position also connects an unbuffered sdout to header j14. this header pin, sdoutub, must be used in lieu of sdout since sdout is buffered and does not go high impedance during other codecs time slots. using the multi-chip scenario, the tsin header pin must be connected to the previous codecs tsout line and the first codecs tsin must be connected, via the header, to fsync. note that when p4 is in the 1chip mode, the sdoutub pin on header j14 is not connected to the sdout pin on the CS4215 and is float- ing. there are two scenarios that must be addressed when connecting the cdb4215 to a dsp: one is when the codec is the master in data mode and the other is when the codec is a slave in data mode. in control mode the codec is always a slave and fsync and sclk must be driven from the dsp. since the evaluation board buffers all the signals between the codec and the dsp, the board must "know" which of the two modes is being used. jumper p3 selects the particular mode. codec master data mode when the codec is to be programmed as a mas- ter in data mode, the direction of fsync and sclk have to be changed between control mode and data mode. in this case the p3 jumper must be set for "m/s" which uses the d/ c signal to control the direction of the buffers (u7) for sclk and fsync. when p3 is set to m/s, the buffers drive the j15 header in data mode and receives fsync and sclk from the header in control mode. codec slave data mode when the codec is to be programmed as a slave in data mode, fsync and sclk are always in- puts to the codec. in this mode p3 must be set to "slave" which configures the fsync and sclk buffers to always receive fsync and sclk from the j15 header. as stated in the CS4215 data sheet, when the codec is programmed in slave mode, xclk = 0 in control mode, sclk and fsync are inputs and must be derived from the same clock used as the master clock for the codec. although sclk and fsync must be frequency locked to the master clock, there is no phase requirement. control pins all control pins, located on header j14, are de- fined as pins that are not essential to the dsp serial port when used in 1chip mode. cdb4215 ds76db3 43
d/c sdout sdin sclk fsync u7 74hct243 p3 m/s slave vd 40 k r49 vd p4 1chip r47 20 k q2,q3 = mpsa14 r53 237 k r30 237 k r54 800 r55 800 q3 q2 d4 d3 2 3 4 5 6 8 11 18 17 16 15 14 12 9 rp1 100 ohm dip 1 2 8 1 16 sdout sdin tsin pdn tsout pio0 rp2 20 k sip d/c u1 CS4215 35 44 1 40 41 13 36 37 multi vd pio1 10 j15 pio0 pio1 7 vd c41 0.1 uf c40 0.1 uf b0 b1 b2 b3 a0 a1 a2 a3 oea 1 oeb 13 r43 1 k r44 1 k 3 4 5 6 11 10 9 8 gnd 14 sclk fsync 43 42 clkout 5 20 713 clkout c49 0.1 uf vd 14 10 9 6 vd d3 in4148 r7 47 k + c15 1 uf reset 4 5 r9 20 k 100 12 r8 reset 8 c42 7 0.1 uf r42 100 tsin tsout sdoutub 8 9 j14 pdn pio0 pio1 reset u4 74htc541 r50 50 u5b u5c figure 4. digital interface cdb4215 44 ds76db3
pdn and reset power down, pdn, controls the pdn pin on the codec. the line has an on-board pull-down resis- tor thereby defining the default state as powered. this pin only needs to be controlled if the power down feature is used. reset controls the reset pin on the codec and is pulled up on the board. this defines the default state as not reset. this pin only needs to be controlled if the reset feature on the codec is needed. since the codec does require a reset at power up, a power-up reset circuit is included on the board. a reset switch is also included to reset the device without having to remove the power supply. the power-up reset plus switch are logi- cally or?ed with the reset pin on header j14. pio lines the parallel input/output, pio, lines are pulled up on the evaluation board. if they are to be used as inputs, they should be driven by open-collec- tor gates since inadvertently setting the pio bits low in software will force the external lines low. the pio lines are available on header j14. the pio lines also go through a high-impedance buffer and drive led?s on the evaluation board. when the led is on, the corresponding bit is 1 or high. the led?s provide a visual indication that may be used to verify that the software is writing the bits correctly. clocks the cdb4215 can accommodate all clocking modes supported by the CS4215. a clkin bnc, as shown in figure 5 allows the clkin pin on the CS4215 to be used as the master clock source. the two crystals listed in the CS4215 data sheet are also provided and support all the audio and multimedia standard sample frequencies. the master clock is selected via a CS4215 internal register from control mode. the clkout bnc is a buffered version of the clkout pin on the CS4215. clkout is al- ways 256 times the programmed sample frequency in data mode. clkout is held low in control mode. layout issues figure 6 contains the silk screen, figure 7 con- tains the top-side copper layer, and figure 8 contains the bottom-side copper layer of the cdb4215 evaluation board. these plots are in- cluded to provide an example of how to layout a pcb for the codec. two of the more important aspects are the position of the ground plane split, which is next to the part - not under it , and the ground plane fill between traces on both lay- ers, which minimizes coupling of radiated energy. u5d 74hc132 vd 13 12 3 1 2 4 clkin 11 clkin 74hc132 u5a r29 5k CS4215 r16 10 k r32 1 k figure 5. clkin cdb4215 ds76db3 45
figure 6. cdb4215 board silkscreen (not to scale) cdb4215 46 ds76db3
figure 7. cdb4215 compont side layout (not to scale) cdb4215 ds76db3 47
figure 8. cdb4215 solder side layout (not to scale) cdb4215 48 ds76db3
e e1 d1 d d2/e2 44 pin plcc no. of terminals d2/e2 max min max min millimeters inches dim a d/e 17.65 17.40 0.685 b e a a1 b e 0.695 16.66 16.51 0.650 0.656 4.57 4.20 0.180 0.165 0.53 0.33 0.021 0.013 2.29 0.090 16.00 14.99 0.590 0.630 1.19 1.35 0.047 0.053 nom 17.53 16.59 4.45 0.41 2.79 15.50 1.27 nom 0.690 0.653 0.175 0.016 0.110 0.610 0.050 3.04 0.120 d1/e1 a1
millimeters inches 0.006 0.618 0.547 0.000 min 0.642 0.555 0.065 max 0.010 1 0.40 0.016 0.012 0.028 0.015 0.025 dim d c b a l e 0 12 0.14 15.70 13.90 0.00 min 0.30 0.375 0 16.30 14.10 1.66 max 0.26 0.70 0.625 12 100 pin tqfp 0.60 0.024 e d1 d 0.618 0.547 0.642 0.555 e 15.70 13.90 16.30 14.10 e b c a1 a l terminal detail 1 0.51 0.20 16.00 14.00 nom 0.51 0.5 16.00 14.00 0.020 0.008 0.630 0.551 nom 0.020 0.020 0.630 0.551 - - -- -- -- -- a1 d1 e1 m m 1.00 bsc 0.039 bsc e1
? notes ?
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